Title: mos sample1

* models

.MODEL MY_NMOS NMOS  VTO=3 KP=0.1
.MODEL MY_PMOS PMOS VTO=-3 KP=0.1

* power

Vpow 100 0 5

* clocks

*Vclk1  1 0 PULSE(0 5  40u 40u 40u 130u 1000u)
Vclk12 2 0 PULSE(0 5  40u 40u 40u 380u 1000u)
*Vclk3  3 0 PULSE(0 5 540u 40u 40u 130u 1000u)
Vclk34 4 0 PULSE(0 5 540u 40u 40u 380u 1000u)

* inverted clocks
Vclk1inv  5 0 PULSE(5 0  40u 40u 40u 130u 1000u)
Vclk12inv 6 0 PULSE(5 0  40u 40u 40u 380u 1000u)
Vclk3inv  7 0 PULSE(5 0 540u 40u 40u 130u 1000u)
*Vclk34inv 8 0 PULSE(5 0 540u 40u 40u 380u 1000u)

* inputs

VinA 10 0 PULSE(0 5   40u 40u 40u  880u 2000u)
VinB 11 0 PULSE(0 5 3040u 40u 40u 1880u 4000u)

* logic gates

*NAND(A,B) type1
M20 20 5 100 100 MY_PMOS
M21 20 2 21 0 MY_NMOS
M22 21 10 22 0 MY_NMOS
M23 22 11 23 0 MY_NMOS
M24 23 5 0 0 MY_NMOS
C20 20 0 1p
C21 21 0 1f
C22 22 0 1f
C23 23 0 1f

*NOR(A,B) type1
M30 30 5 100 100 MY_PMOS
M31 30 2 31 0 MY_NMOS
M32 31 10 32 0 MY_NMOS
M33 31 11 32 0 MY_NMOS
M34 32 5 0 0 MY_NMOS
C30 30 0 1p
C31 31 0 1f
C32 32 0 1f

*NOT(NAND(A,B)) type2
M40 40 6 100 100 MY_PMOS
M41 40 20 41 0 MY_NMOS
M42 41 6 0 0 MY_NMOS
C40 40 0 1p
C41 41 0 1f

*NOR(NOR(A,B),NOT(NAND(A,B)) type3
M50 50 7 100 100 MY_PMOS
M51 50 4 51 0 MY_NMOS
M52 51 30 52 0 MY_NMOS
M53 51 40 52 0 MY_NMOS
M54 52 7 0 0 MY_NMOS
C50 50 0 1p
C51 51 0 1f
C52 52 0 1f

* simulation

.TRAN 10u 5m 1m

* result output

*.PRINT TRAN I(Vpow)
.PRINT TRAN V(20) V(30) V(40) V(50)

.END