Title: mos sample2

* models

.MODEL MY_NMOS NMOS VTO=1 KP=0.1
*.MODEL MY_PMOS PMOS VTO=-1 KP=0.1

* clocks

Vclk1  1 0 PULSE(0 10 40u 40u 40u 130u 1000u)
Vclk12 2 0 PULSE(0 10 40u 40u 40u 380u 1000u)
Vclk3  3 0 PULSE(0 10 540u 40u 40u 130u 1000u)
Vclk34 4 0 PULSE(0 10 540u 40u 40u 380u 1000u)

* inputs

VinA 10 0 PULSE(0 10 40u 40u 40u 880u 2000u)
VinB 11 0 PULSE(0 10 3040u 40u 40u 1880u 4000u)

* logic gates

*NAND(A,B) type1
M20 1 1 20 0 MY_NMOS
M21 20 2 21 0 MY_NMOS
M22 21 10 22 0 MY_NMOS
M23 22 11 1 0 MY_NMOS
C20 20 0 1p
C21 21 0 1f
C22 22 0 1f

*NOR(A,B) type1
M30 1 1 30 0 MY_NMOS
M31 30 2 31 0 MY_NMOS
M32 31 10 1 0 MY_NMOS
M33 31 11 1 0 MY_NMOS
C30 30 0 1p
C31 31 0 1f

*NOT(NAND(A,B)) type2
M40 1 1 40 0 MY_NMOS
M41 40 20 41 0 MY_NMOS
M42 41 3 1 0 MY_NMOS
C40 40 0 1p
C41 41 0 1f

*NOR(NOR(A,B),NOT(NAND(A,B)) type3
M50 3 3 50 0 MY_NMOS
M51 50 4 51 0 MY_NMOS
M52 51 30 3 0 MY_NMOS
M53 51 40 3 0 MY_NMOS
C50 50 0 1p
C51 51 0 1f

* simulation

.TRAN 1u 5m 1m

* result output

.PRINT TRAN V(20) V(30) V(40) V(50)

.END