＞トップ

CORDIC 関係のメモ

参考文献

順不同

• http://en.wikipedia.org/wiki/CORDIC
• 「アルゴリズム辞典」, "CORDIC", pp. 257〜258
• （連載: 算術演算回路のアルゴリズム）「4. 初等関数演算回路のアルゴリズム」―専用回路の実現に向けて―, 情報処理学会学会誌「情報処理」, Vol. 37 No. 4 (Apr. 1996), pp. 362〜368
• （「算術演算のVLSIアルゴリズム」上記連載の単行本化）
• CORDIC による三角関数の計算 (冨永丈博さん) http://www.initialt.org/float/cordic.html

SFL による実装

• cordic_sfl.tar.bz2

======== 00README.txt
   CORDIC sample implementation in SFL

     by KISHIMOTO, Makoto


Copyright

  Copyright (c) 2009 KISHIMOTO, Makoto

  Permission is hereby granted, free of charge, to any person obtaining a copy
  of this software and associated documentation files (the "Software"), to deal
  in the Software without restriction, including without limitation the rights
  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  copies of the Software, and to permit persons to whom the Software is
  furnished to do so, subject to the following conditions:

  The above copyright notice and this permission notice shall be included in
  all copies or substantial portions of the Software.

  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  THE SOFTWARE.


Manifest

  00README.txt             this file
  Makefile                 makefile
  cla32.sfl                adder (stub)
  cordic32.sfl             CORDIC sample implementation by SFL
  cordic32_test.v          Verilog script for test
  inc5.h                   5 bits incrementer SFL header
  inc5.sfl                 5 bits incrementer SFL
  inc5_test.v              Verilog script for test
  serial_rom.h             arctangent table rom SFL header
  serial_rom.sfl           arctangent table rom SFL
  serial_rom_test.v        Verilog script for test
  sft32.sfl                shifter (stub)
  theta.dat                angle data for test


About SFL processor

  Requires these SFL processors.

  * PARTHENON System (NTT)
    - http://www.kecl.ntt.co.jp/parthenon/html/download_j.htm
    - http://www-lab09.kuee.kyoto-u.ac.jp/parthenon/distribution/index.html
  * sfl2vl (ip-arch) version>=20090922 http://www.ip-arch.jp/sfl2vl.html

  * (Icarus Verilog (Verilog HDL processor))


Warning in converting

  These are known warning.

  cordic32.sfl

  > cordic32.sfl:67: Warning: one pin net _sft32_y_srl is forced to set 0
  >  near (})
  > cordic32.sfl:67: Warning: one pin net _sft32_y_sll is forced to set 0
  >  near (})
  > cordic32.sfl:67: Warning: one pin net _sft32_x_srl is forced to set 0
  >  near (})
  > cordic32.sfl:67: Warning: one pin net _sft32_x_sll is forced to set 0
  >  near (})

  cla32.sfl

  > /usr/local/parthenon/sfl_lib.dir/cla32.cir:11: Warning: Operand width unmatch for +  near (})


About fixed-point format

          <----------- 32 ------------->
          |     |     | . . . . . . . .|
   wait     -2     1  . 0.5 0.25 ...
          (sign)      `radix point

  Input value of angle is radian. The range is about from -1.6 to +1.6 .
========